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2. Contador de 0 a 9 con display de 7 segmentos (Ver Inglés)

The purpose of this project is to implement a counter from 0 to 9 in VHDL using a common cathode 7-segment display using Symbhia. 
The counter is controlled by 1 start/stop bit and a reset bit. The count increment is 1s (Time that can be changed by modifying the constant END_DELAY in the code).


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Ports used in practice:

  • CLK (Input – 1 bit): Clock at 50MHz.
  • INI (Input – 1 bit): Start bit connected to a switch on Symbhia. When INI is set to ‘1’ it starts counting, when it is set to ‘0’ it stops counting.
  • RESET (Input – 1 bit): Reset bit connected to a switch on Symbhia. When RESET is ‘1’, the count is reset.
  • DISPLAY (Output – 7 bits): 7-bit output connected to the 7-segment display.

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